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HM62V16100I Series
Wide Temperature Range Version 16 M SRAM (1-Mword x 16-bit)
REJ03C0060-0200Z Rev. 2.00 Oct.06.2003
Description
The HM62V16100I Series is 16-Mbit static RAM organized 1-Mword x 16-bit. HM62V16100I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has the package variations of 48-bump chip size package with 0.75 mm bump pitch and 48-pin plastic TSOPI for high density surface mounting.
Features
* Single 3.0 V supply: 2.7 V to 3.6 V * Fast access time: 45/55 ns (max) * Power dissipation: Active: 9 mW/MHz (typ) Standby: 1.5 W (typ) * Completely static memory. No clock or timing strobe required * Equal access and cycle times * Common data input and output. Three state output * Battery backup operation. 2 chip selection for battery backup * Temperature range: -40 to +85C
Rev.2.00, Oct.06.2003, page 1 of 23
HM62V16100I Series
Ordering Information
Type No. HM62V16100LTI-4 HM62V16100LTI-4SL HM62V16100LTI-5SL HM62V16100LBPI-4 HM62V16100LBPI-4SL HM62V16100LBPI-5SL Access time 45 ns 45 ns 55 ns 45 ns 45 ns 55 ns 48-bump CSP with 0.75 mm bump pitch (TBP-48F) Package 48-pin plastic TSOPI (normal-bend type) (TFP-48DA)
Rev.2.00, Oct.06.2003, page 2 of 23
HM62V16100I Series
Pin Arrangement
48-pin TSOP A15 A14 A13 A12 A11 A10 A9 A8 A19 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Top view) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16
BYTE
VSS I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0
WE
CS2 NU
UB LB
A18 A17 A7 A6 A5 A4 A3 A2 A1
OE
VSS
CS1
A0
Rev.2.00, Oct.06.2003, page 3 of 23
HM62V16100I Series
Pin Description (TSOP)
Pin name A0 to A19 A-1 to A19 I/O0 to I/O15 CS1 CS2 WE OE LB UB BYTE VCC VSS NC NU*
1
Function Address input (word mode) Address input (byte mode) Data input/output Chip select 1 Chip select 2 Write enable Output enable Lower byte select Upper byte select Byte enable Power supply Ground No connection Not used (test mode pin)
Note: 1. This pin should be connected to a ground (VSS), or not be connected (open).
Rev.2.00, Oct.06.2003, page 4 of 23
HM62V16100I Series
48-bumps CSP
1 A
2
3
A0
4
A1
5
A2
6
CS2
LB
I/O8
OE UB
I/O10
B
A3
A4
CS1
I/O1
I/O0
C
I/O9
A5
A6
I/O2
D
VSS
I/O11
A17
A7
I/O3
VCC
E
VCC
I/O12
VSS
A16
I/O4
VSS
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
A19
A12
A13
WE
A11
I/O7
H
A18
A8
A9
A10
NU
(Top view)
Pin Description (CSP)
Pin name A0 to A19 I/O0 to I/O15 CS1 CS2 WE OE LB UB VCC VSS NU*
1
Function Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Lower byte select Upper byte select Power supply Ground Not used (test mode pin)
Note: 1. This pin should be connected to a ground (VSS), or not be connected (open).
Rev.2.00, Oct.06.2003, page 5 of 23
HM62V16100I Series
Block Diagram (TSOP)
LSB
A15 A14 A13 A12 A11 A10 A9 A8 A18 A16 A19 A4 A5
V CC V SS
Row decoder
* * * * *
Memory matrix 8,192 x 128 x 16 8,192 x 256 x 8
MSB
I/O0 Input data control I/O15
* *
Column I/O Column decoder
* *
MSBA17 A7A6 A3 A2 A1A0 A-1 LSB
* *
BYTE CS1 LB UB WE OE
CS2 Control logic
Rev.2.00, Oct.06.2003, page 6 of 23
HM62V16100I Series
Block Diagram (CSP)
LSB A19 A8 A9 A10 A11 A12 A13 A14 A16 A18 A15 A3 MSB A6
V CC V SS
Row decoder
* * * * *
Memory matrix 8,192 x 128 x 16
I/O0 Input data control I/O15
* *
Column I/O Column decoder
* *
MSB A17 A7 A5 A4 A2 A1 A0 LSB
* *
CS1 LB UB WE OE
CS2 Control logic
Rev.2.00, Oct.06.2003, page 7 of 23
HM62V16100I Series
Operation Table (TSOP)
Byte mode
CS1 CS2 WE H x L L L x L H H H x x H L H OE x x L x H UB x x x x x LB x x x x x BYTE L L L L L I/O0 to I/O7 High-Z High-Z Dout Din High-Z I/O8 to I/O14 I/O15 High-Z High-Z High-Z High-Z High-Z High-Z High-Z A-1 A-1 High-Z Operation Standby Standby Read Write Output disable
Note: H: VIH, L: VIL, x: VIH or VIL
Word mode
CS1 CS2 WE H x x L L L L L L L x L x H H H H H H H x x x H H H L L L H OE x x x L L L x x x H UB x x H L H L L H L x LB x x H L L H L L H x BYTE H H H H H H H H H H I/O0 to I/O7 High-Z High-Z High-Z Dout Dout High-Z Din Din High-Z High-Z I/O8 to I/O14 I/O15 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z Operation Standby Standby Standby Read Lower byte read Upper byte read Write Lower byte write Upper byte write Output disable
Note: H: VIH, L: VIL, x: VIH or VIL
Rev.2.00, Oct.06.2003, page 8 of 23
HM62V16100I Series
Operation Table (CSP)
CS1 H x x L L L L L L L CS2 x L x H H H H H H H WE x x x H H H L L L H OE x x x L L L x x x H UB x x H L H L L H L x LB x x H L L H L L H x I/O0 to I/O7 High-Z High-Z High-Z Dout Dout High-Z Din Din High-Z High-Z I/O8 to I/O15 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z Operation Standby Standby Standby Read Lower byte read Upper byte read Write Lower byte write Upper byte write Output disable
Note: H: VIH, L: VIL, x: VIH or VIL
Absolute Maximum Ratings
Parameter Power supply voltage relative to VSS Terminal voltage on any pin relative to VSS Power dissipation Storage temperature range Storage temperature range under bias Symbol VCC VT PT Tstg Tbias Value -0.5 to +4.6 -0.5* to VCC + 0.3*
1 2
Unit V V W C C
1.0 -55 to +125 -40 to +85
Notes: 1. VT min: -2.0 V for pulse half-width 10 ns. 2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range Note: VIH VIL Ta Min 2.7 0 2.2 -0.3 -40 Typ 3.0 0 Max 3.6 0 VCC + 0.3 0.6 +85 Unit V V V V C 1 Note
1. VIL min: -2.0 V for pulse half-width 10 ns.
Rev.2.00, Oct.06.2003, page 9 of 23
HM62V16100I Series
DC Characteristics
Parameter Input leakage current Output leakage current Symbol Min |ILI| |ILO| Typ*
1
Max 1 1
Unit A A
Test conditions* Vin = VSS to VCC
2
CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL or LB = UB = VIH, VI/O = VSS to VCC CS1 = VIL, CS2 = VIH, Others = VIH/ VIL, II/O = 0 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1 = VIL, CS2 = VIH, WE = VIH, Others = VIH/VIL Min. cycle, duty = 100%, II/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/VIL Cycle time = 70 ns, duty = 100%, II/O = 0 mA, CS1 = VIL, CS2 = VIH, WE = VIH, Others = VIH/VIL Address increment scan or decrement scan Cycle time = 70 ns, duty = 100%, II/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/VIL Address increment scan or decrement scan Cycle time = 1 s, duty = 100%, II/O = 0 mA, CS1 0.2 V, CS2 VCC - 0.2 V VIH VCC - 0.2 V, VIL 0.2 V CS2 = VIL 0 V Vin (1) 0 V CS2 0.2 V or (2) CS1 VCC - 0.2 V, CS2 VCC - 0.2 V or (3) LB = UB VCC - 0.2 V, CS2 VCC - 0.2 V, CS1 0.2 V Average value IOH = -1 mA IOH = -100 A IOL = 2 mA IOL = 100 A
Operating current Average operating current
ICC ICC1 (READ) ICC1

22
20 35
mA mA
30
50
mA
ICC2* (READ)
5
3
8
mA
ICC2
*5
20
30
mA
ICC3
3
8
mA
Standby current Standby current
ISB ISB1*
3

0.1 0.5
0.5 25
mA A
ISB1* Output high voltage VOH VOH Output low voltage VOL VOL
4
2.4
0.5
8 0.4 0.2
A V V V V
VCC - 0.2
Rev.2.00, Oct.06.2003, page 10 of 23
HM62V16100I Series
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 2. BYTE pin supported by only TSOP type. BYTE VCC - 0.2 V or BYTE 0.2 V 3. This characteristic is guaranteed only for L-version. 4. This characteristic is guaranteed only for L-SL version. 5. ICC2 is the value measured while the valid address is increasing or decreasing by one bit. Word mode: LSB (least significant bit) is A0. Byte mode: LSB (least significant bit) is A-1.
Capacitance
(Ta = +25C, f = 1.0 MHz)
Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min Typ Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1
1. This parameter is sampled and not 100% tested.
Rev.2.00, Oct.06.2003, page 11 of 23
HM62V16100I Series
AC Characteristics
(Ta = -40 to +85C, VCC = 2.7 V to 3.6 V, unless otherwise noted.) Test Conditions * Input pulse levels: VIL = 0.4 V, VIH = 2.4 V * Input rise and fall time: 5 ns * Input and output timing reference levels: 1.4 V * Output load: See figures (Including scope and jig)
1.4 V
RL=500 Dout 50pF
Rev.2.00, Oct.06.2003, page 12 of 23
HM62V16100I Series Read Cycle
HM62V16100I -4 Parameter Read cycle time Address access time Chip select access time Symbol tRC tAA tACS1 tACS2 Output enable to output valid Output hold from address change LB, UB access time Chip select to output in low-Z LB, UB enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB, UB disable to high-Z Output disable to output in high-Z tOE tOH tBA tCLZ1 tCLZ2 tBLZ tOLZ tCHZ1 tCHZ2 tBHZ tOHZ Min 45 10 10 10 5 5 0 0 0 0 Max 45 45 45 30 45 20 20 15 15 -5 Min 55 10 10 10 5 5 0 0 0 0 Max 55 55 55 35 55 20 20 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes
Write Cycle
HM62V16100I -4 Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width LB, UB valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Write to output in high-Z Symbol tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ Min 45 45 45 35 45 0 0 25 0 5 0 0 Max 15 15 -5 Min 55 50 50 40 50 0 0 25 0 5 0 0 Max 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2 1, 2 1, 2 6 7 5 4 Notes
Rev.2.00, Oct.06.2003, page 13 of 23
HM62V16100I Series Byte Control
HM62V16100I -4 Parameter BYTE setup time BYTE recovery time Symbol tBS tBR Min 5 5 Max -5 Min 5 5 Max Unit ms ms Notes 8 8
Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1, a high CS2, a low WE and a low LB or a low UB. A write begins at the latest transition among CS1 going low, CS2 going high, WE going low and LB going low or UB going low. A write ends at the earliest transition among CS1 going high, CS2 going low, WE going high and LB going high or UB going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1 going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle. 8. Byte control supported by only TSOP type.
Rev.2.00, Oct.06.2003, page 14 of 23
HM62V16100I Series
Timing Waveform
Read Cycle*
1
t RC Address*2 tAA tACS1 Valid address
CS1
tCLZ1 tCHZ1
CS2
tACS2 tCLZ2 tCHZ2 tBHZ tBA
LB, UB
tBLZ tOE tOHZ
OE
tOLZ Dout*3 High impedance Valid data tOH
Notes: 1. Only for TSOP type. BYTE > VCC - 0.2 V or BYTE < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7
Rev.2.00, Oct.06.2003, page 15 of 23
HM62V16100I Series Write Cycle (1)* (WE Clock)
tWC Address*2 Valid address tWR
1
tCW
CS1
tCW CS2 tBW
LB, UB
tAW tWP
WE
tAS tDW tDH
Din*3 tWHZ
Valid data tOW High impedance
Dout*3
Notes: 1. Only for TSOP type. BYTE > VCC - 0.2 V or BYTE < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7
Rev.2.00, Oct.06.2003, page 16 of 23
HM62V16100I Series Write Cycle (2)* (CS1, CS2 Clock, OE = VIH)
1
tWC Address*2 tAS Valid address tAW tCW tWR
CS1
tAS CS2 tBW tCW
LB, UB
tWP
WE
tDW Din*3 Valid data
tDH
Dout*3
High impedance
Notes: 1. Only for TSOP type. BYTE > VCC - 0.2 V or BYTE < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7
Rev.2.00, Oct.06.2003, page 17 of 23
HM62V16100I Series Write Cycle (3)* (LB, UB Clock, OE = VIH)
1
tWC Address Valid address tAW tCW
CS1
tWR
tCW CS2 tAS
UB
tBW
(LB) tBW
LB
(UB)
tWP
WE
tDW Din-UB (Din-LB) Valid data tDW
tDH
tDH
Din-LB (Din-UB) Dout Note: 1. Only for TSOP type. BYTE > V CC - 0.2 V
Valid data
High impedance
Rev.2.00, Oct.06.2003, page 18 of 23
HM62V16100I Series Byte Control (TSOP)
CS2
+5 *;6-
tBS
tBR
Rev.2.00, Oct.06.2003, page 19 of 23
HM62V16100I Series
Low VCC Data Retention Characteristics
(Ta = -40 to +85C)
Parameter VCC for data retention Symbol VDR Min 1.5 Typ*
5
Max 3.6
Unit V
Test conditions*
3, 4
Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 VCC - 0.2 V, CS1 VCC - 0.2 V or (3) LB = UB VCC - 0.2 V, CS2 VCC - 0.2 V, CS1 0.2 V VCC = 3.0 V, Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 VCC - 0.2 V, CS1 VCC - 0.2 V or (3) LB = UB VCC - 0.2 V, CS2 VCC - 0.2 V, CS1 0.2 V Average value
Data retention current
ICCDR*
1
0.5
25
A
ICCDR* Chip deselect to data retention time Operation recovery time tCDR tR
2
0 5
0.5
8
A ns ms See retention waveforms
Notes: 1. This characteristic is guaranteed only for L-version. 2. This characteristic is guaranteed only for L-SL version. 3. BYTE pin supported by only TSOP type. BYTE VCC - 0.2 V or BYTE 0.2 V 4. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, LB, UB buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, LB, UB, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 VCC - 0.2 V or 0 V CS2 0.2 V. The other input levels (address, WE, OE, LB, UB, I/O) can be in the high impedance state. 5. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed.
Rev.2.00, Oct.06.2003, page 20 of 23
HM62V16100I Series Low VCC Data Retention Timing Waveform (1) (CS1 Controlled)
t CDR V CC 2.7 V Data retention mode tR
2.2 V V DR
+5
0V
CS1 VCC - 0.2 V
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
t CDR V CC 2.7 V CS2 V DR 0.6 V 0V 0 V < CS2 < 0.2 V Data retention mode tR
Low VCC Data Retention Timing Waveform (3) (LB, UB Controlled)
t CDR V CC 2.7 V Data retention mode tR
2.2 V V DR
LB, UB
0V
LB, UB VCC - 0.2 V
Rev.2.00, Oct.06.2003, page 21 of 23
HM62V16100I Series
Package Dimensions
HM62V16100LTI Series (TFP-48DA)
12.00 12.40 Max 48
As of January, 2003
Unit: mm
25
1 0.50 *0.22 0.08 0.08 M 0.20 0.06 0.45 Max
1.20 Max
24
*0.17 0.05 0.125 0.04
18.40
0.80 20.00 0.20 0 - 8
0.05 0.05
0.50 0.10
Package Code JEDEC JEITA Mass (reference value) TFP-48DA Conforms Conforms 0.52 g
0.10
*Dimension including the plating thickness Base material dimension
Rev.2.00, Oct.06.2003, page 22 of 23
HM62V16100I Series HM62V16100LBPI Series (TBP-48F)
As of January, 2003
Unit: mm
0.20 S B
0.20 S A
2.125
8.00
A
6 5 4 3
A 2 1
INDEX MARK
Pin#1 INDEX
A B C B
9.50
D E F G
0.75
H
4x
0.15
0.75
2.125
0.2 S
S
48 x 0.35 0.05 0.08 M S A B
0.25 0.05
0.10 S
1.2 Max
Details of the part A
Package Code JEDEC JEITA Mass (reference value)
TBP-48F - - 0.15 g
Rev.2.00, Oct.06.2003, page 23 of 23
Revision History
Rev. Date
HM62V16100I Series Data Sheet
Contents of Modification Page Description Initial issue Deletion of Preliminary Deletion of HM62V16100LTI-5, HM62V16100LBPI-5
0.0 1.00 2.00
Sep. 21, 2001 Jun.19, 2003 Oct.06, 2003
Sales Strategic Planning Div.
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